下列Moore型状态机采用Verilog语言说明部分正确的是:
A、parameter [2:0] s0=0, s1=1,s2=2,s3=3,s4=4; reg [2:0] current_state, next_state;
B、parameter [1:0] s0=0, s1=1,s2=2,s3=3,s4=4; reg [1:0] current_state, next_state;
C、TYPE FSM_ST IS (s0, s1,s2,s3,s4); SIGNAL current_state, next_state: FSM_ST;
D、typedef enum {s0, s1,s2,s3,s4} type_user; type_user current_state, next_state